The present invention relates to dynamic random access memories with reduced power consumption, and in particular, to a low power consumption type suitable for use in a cellular phone or the like.
Because a dynamic random access memory (referred to hereinafter as a DRAM) is provided with memory cells made up of a transistor and a capacitor, the DRAM can be highly integrated. Accordingly, its price is lower in comparison with other random access memories, particularly a static random access memory (referred to hereinafter as SRAM).
Meanwhile, current consumption of the SRAM is lower in comparison with that of the DRAM, and in particular, current consumption of the SRAM at standby times when read/write are not performed is markedly lower in comparison with that for the DRAM. One of reasons for this is that the DRAM performs refresh operation during standby to hold data.
The DRAM is usually driven by a power supply from outside (an external power supply), and when supply of power from the external power supply is cut off, data held in the DRAM are erased. This is because the refresh operation described above can not be performed, so that stored data can not be held. Further, internal circuits of the DRAM are not driven by direct use of the external power supply, but usually voltage of the external power supply is converted into internal voltage through an internal voltage generation circuit, thereby driving respective circuits with the internal voltage.
The DRAM described above is useful in equipment such as a personal computer with constant supply of voltage from an eternal power supply, but not suitable for use in a device such as a cellular phone, and so forth, of which low current consumption is required. Accordingly, a conventional cellular phone has a memory configuration wherein a controller 20, a SRAM 30, and a flash memory 40 are connected to a data bus 10 in common, as shown in FIG. 2, and voltage from a power supply 50 is supplied to these components all the time.
There has recently been seen a trend of the cellular phone transmitting and receiving not only voice but also massive data such as character information, picture data, and so forth. The DRAM has a large storage capacity, however, it consumes current by performing refresh operation, and usually has a circuit configuration comprising a circuit for generating an internal potential, wherein current is constantly consumed. For this reason, the DRAM is unsuitable for use in the device such as the cellular phone, and so forth, of which low current consumption is required. As described above, the conventional cellular phone has the memory configuration wherein the controller 20, the SRAM 30, and the flash memory 40 are connected to the data bus 10 in common, as shown in FIG. 2, and the voltage from the power supply 50 is supplied to these components all the time.
As described in the foregoing, since the DRAM has large current consumption, it is necessary to hold down current consumption thereof when put to use in the cellular phone. Accordingly, adoption of a configuration as shown in FIG. 3 is conceivable in case of using the DRAM in the cellular phone. More specifically, as with the SRAM 30, and the flash memory 40, a DRAM 60 is connected to the data bus 10, however, a switch 70 is provided between the power supply 50 and the DRAM 60. The controller 20 makes a decision on necessity of using the DRAM 60, and holds down current consumption in the DRAM 60 by cutting off supply of voltage from the power supply 50 with the flick of the switch 70 (by tuning off the switch 70) when a negative decision is made.
With the configuration shown in FIG. 3, however, there will arise problems that (1) an external element such as the switch 70 is required, and (2) there is a possibility of the DRAM 60 undergoing malfunction due to flow-in of current from the data bus 10 through a parasitic diode when supply of power from the power supply 50 to the DRAM 60 is cut off. The problem (2) of these problems will be described in detail hereinafter with reference to FIG. 4.
To take an example wherein the final stage of an output circuit of the DRAM 60 is an inverter, an inverter 100 is made up of an NMOS transistor 110 and a PMOS transistor 120 as shown in FIG. 4. The gate of the NMOS transistor 110 and the gate of the PMOS transistor 120 are connected to an input node 150 in common. In the case of the output circuit, the input node 150 receives an output signal from the DRAM 60. The source S of the PMOS transistor 120 is provided with a power supply potential. The drain D of the PMOS transistor 120 and the drain of the NMOS transistor 110 are connected to an output node 140 in common. The output node 140 is connected to an output terminal of the DRAM 60, and to the data bus 10 as shown in FIG. 3 in the case where the DRAM 60 is mounted in the cellular phone, or the like. The source of the NMOS transistor 110 is provided with the ground potential.
Herein, in the PMOS transistor 120, there is formed a parasitic diode 130 forward biased from the drain D of the PMOS transistor 120 to the source S thereof. When supply of power is cut off, and voltage is no longer supplied to the source S of the PMOS transistor 120, the source S of the PMOS transistor 120 is not provided with the power supply potential. Meanwhile, when a signal at a high (H) level is sent to the data bus 10, the signal at the H level is given to the drain D of the PMOS transistor 120 because the DRAM 60 is connected to the data bus 10. Consequently, the H level signal is given to the source S of the PMOS transistor 120 via the parasitic diode 130. Because the source S of the PMOS transistor 120 is connected to other circuits via a power supply line, it follows that the other circuits are supplied with a potential. Further, with reference to data on the data bus, there is a possibility of the level of the H level signal being lowered to a low (L) level.
The invention has been developed to solve the problems described above, and it is an object of the invention to provide a low power consumption type dynamic random access memory (DRAM) with reduced current consumption in the DRAM by a signal from outside, and without causing occurrence of malfunction at times of low current consumption.
A low power consumption type dynamic random access memory according to the invention comprises internal voltage receiving circuits driven by an external power supply, for generating internal voltages, an input circuit for receiving signals, a memory array for holding data peripheral circuit for controlling the memory array, and an output circuit for outputting signals, wherein the output circuit is driven by the external power supply while the input circuit, the memory array, and the peripheral circuit are driven by the internal voltages generated by the internal voltage receiving circuits, respectively, and the internal voltage receiving circuits are deactivated in response to a control signal inputted from outside, the output circuit being controlled so as to be in a high impedance condition with the voltage of the external power supply being applied thereto.